The present invention relates to a serial communication system and, more particularly, to a synchronizer for locating a frame boundary in a serial data stream.
In a typical serial communication system, data is transferred to a data stream receiver in sets of multi-bit frames. The data stream receiver includes a frame synchronizer which locates the frame boundaries and then synchronizes the receipt of information to the frame boundaries. This allows the receiver to accurately extract and process the received data. For example, a "T1" data stream is formed of a set of 193-bit frames. Each frame in the set includes one frame bit and 192 payload bits. The frame bit is located at a particular location in each frame. The payload bits can include encoded voice data, for example. A T1 data stream is transmitted in a selected format, such as Extended Super Frame (ESF) format or Super Frame (SF) format. In ESF format, data is collected in sets of 24 frames and transmitted as a continuous stream. In SF format, data is collected in sets of 12 frames and transmitted as a continuous stream. Of the 24 frame bits per set in the ESF format and the 12 frame bits per set in the SF format, six frame bits are used for frame boundary identification. These frame boundary bits are referred to as "FPS" bits in the ESF format and "Ft" bits in the SF format. The remaining frame bits are used for other purposes, such as data link bits or for Cyclic Redundancy Checks ("CRCs").
The six frame boundary bits together form a predetermined pattern, beginning with the first frame boundary bit of the set. The data stream receiver locates the frame boundary bits, and thus the boundaries between the data frames, by searching the received data stream for the predetermined pattern. A typical data stream receiver considers a number of consecutive frame boundary bits that follow a particular bit position before declaring the bit position as a possible boundary. For example, with a 24-bit qualification, the receiver will search for a bit position from which 24 consecutive frame boundary bits have been found.
In one search method, the received data stream is shifted into a large shift register. The shift register has 24 output taps spaced 193 bits apart. The first tap is typically at the first bit position in the shift register. As each bit is written into the shift register, the bits at the 24 output taps are compared to the search pattern. If there is a match, then the first bit position is a possible candidate for a frame boundary. Once a frame boundary has been located, the receiver can lock onto the received data.
A disadvantage of this method is that it requires an enormous amount of storage space. In order to compare 24 bits, the shift register must store four sets of 24 frames, with 193 bits per frame. This requires a shift register capable of holding 18,528 bits. Also, the search process may end in an incorrect result. Because the received data is random in nature, there may be more than one bit position where 24 consecutive frame boundary bits are found. This method validates the first bit position that it encounters with 24-bit qualification, and does not eliminate mimic or false patterns.